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2016年12月14日 星期三

Read DDR4 SPD over 256 byte (switch page)

They have 2 pages of 256 bytes each, and you need a dummy write to a special predefined address 0x6E to switch all SPD chips to page 1 (where your byte 320 is located), and than write to 0x6C switch them back to page 0 (to prevent an SPD read failure during next boot). Read this datasheet on page 12 for more info.

//Dummy cmd to switch
offset 00 write 0xFE to Clear status
offset 04 write 0x6E to switch to page1 (bit 0  : Read/Write , 0:write , 1:Read ))
offset 02 write 0x48 Byte Read (Host Control Register) bit 4:2 => 010 => byte Data , bit 6 : Start
offset00 should be 44 or 42



//Normal read SPD data from page1 - index 40h
offset 00 下 0xFF Clear status
offset 04 下 0xA1 ( bit 7-1 : Slave Address , bit 0  : R/w 0:write , 1:Read )
offset 03 下 0x40 (Host Command Register) index
offset 02 下 0x48 (Host Control Register) bit 4:2 => 010 => byte Data , bit 6 : Start
offset00 should be 0x42 success

42h= 01000010b
     - ->INTR(bit 1)
     |->INUSE_STS(bit 6)

INUSE bit (bit 6)

Bit 7 (DS) default : 0

  • 0 = After a full PCI reset, a read to this bit returns a 0. 

Bit 6 (INUSE_STS) default : 0

  • 0 = Interrupt or SMI# was not generated by SMBALERT#. This bit is only cleared by software writing a 1 to the bit position or by RSMRST# going low. 

 Bit 5 (SMBALERT_STS) default : 0

  •  0 = Cleared by writing a 1 to the bit position. 

 Bit 4 (FAILED) default : 0

  •  0 = Cleared by writing a 1 to the bit position. 


 Bit 3 (BUS_ERR) default : 0

  • 0 = Cleared by writing a 1 to the bit position. 

 Bit 2 (DEV_ERR) default : 0

  • 0 = Software resets this bit by writing a 1 to this location. 

 Bit 1 (INTR) default : 0

  • 0 = Software resets this bit by writing 1 to this location.

Bit 0 (HOST_BUSY) default  0


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